Simple RLC circuit
This example shows a simple series of a voltage source with
resistor, inductor, and capacitor. Because of phasor description,
all results have constant values.
Simulate for an arbitrary time interval (e.g. 1 s).
Plot in seperate windows
- V.v, R.v,
L.v, and C.v
versus "Time"
- V.phi_v, R.phi_v,
L.phi_v, and
C.phi_v versus "Time"
to see the corresponding steady-state values.
Main Author:
Olaf Enge-Rosenblatt
Fraunhofer IIS/EAS, Dresden
email: olaf.enge@eas.iis.fraunhofer.de
Generated at 2026-04-14T18:18:34Z by OpenModelicaOpenModelica 1.26.3 using
GenerateDoc.mos