Model of a n-bit NAND
Description
Model of a n bit NAND gate.
The number of the input (nInput)
signals must be higher than 2, while the number of output
(nOutput) signals is equal to 1.
Depending on the value of the sampling time (Ts), the model has two different behaviours:
-
Ts > 0
it behaves as a discrete time system,
-
Ts <= 0
it behaves as a continous time system. No delay is introduced and
events are generated when the output changes (this mode reduces the
simulation time)
- First release of the Industrial Control Systems: April-May
2012
-
- List of revisions:
-
- 11 May 2012 (author: Marco Bonvini)
- Main Authors:
- Marco Bonvini; <bonvini@elet.polimi.it>
- Alberto Leva <leva@elet.polimi.it>
- Politecnico di Milano
- Dipartimento di Elettronica e Informazione
- Via Ponzio 34/5
- 20133 Milano - ITALIA -
- Copyright:
- Copyright © 2010-2012, Marco Bonvini and Alberto
Leva.
- The IndustrialControlSystems package is free
software; it can be redistributed and/or modified under the terms
of the Modelica license, see the license conditions and the
accompanying disclaimer in the documentation of package
Modelica in file "Modelica/package.mo".
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