typeClockEdge
Edge of the clock on which the data of a synchronous link is read
Information
Sampling edge of a SyncData channel of Peripherals.Analyzers.LogicAnalyzer: the data line is read at this edge of its clock channel. An HX711 changes DOUT on the rising edge of PD_SCK, its data is read on the falling edge; SPI in mode 0 is read on the rising edge.
Literals
| Name | Description |
|---|---|
| Rising | Data read when the clock rises |
| Falling | Data read when the clock falls (HX711: the data is valid before the falling edge) |